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Description: FIR的优化设计 基于CSD码量化 提出了一种降低滤波器运算量的改进方法-Optimal design of FIR based on CSD code to quantify a lower filter to improve the method of computing the amount of
Platform: | Size: 791552 | Author: lvxiaobing | Hits:

[VHDL-FPGA-Verilogfilter1

Description: 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hope it would be useful
Platform: | Size: 13312 | Author: 万勇 | Hits:

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